1. Field of the Invention
The invention relates generally to packaging techniques for integrated circuit devices. More particularly, the invention relates to three dimensional chip packages and packaging techniques which achieve both high volumetric packaging and high cooling efficiency to enhance the performance of a packaged system.
2. Brief Description of the Related Art
Packaging is increasingly the limiting factor in achieving maximum performance from Very Large Scale Integrated (VLSI) based computer systems. The limitations due to packaging arise from two major physical constraints; the maximum power density that can be cooled and the signal transit delay introduced by the package.
Conventional packages fall into two primary categories; two dimensional packages such as planar based systems and three dimensional packages such as card-on-board packages.
The planar type package is used in high end systems to allow for maximum cooling efficiency. In order to increase circuit density in planar packages (and thereby minimize signal transit delay), semiconductor manufacturers have continued to reduce the size of various integrated circuit elements and interconnections to the point where the limits of current technology are being reached.
In order to increase circuit density and gain other manufacturing advantages, various methods have been explored to interconnect a plurality of integrated circuit chips using horizontal and vertical stacking techniques and three dimensional interconnect modules which increase integrated circuit surface are by factors of 2, 3, 4 or more.
Prior art three dimensional packaging schemes are typified by the teachings of Golubic in U.S. Pat. No. 4,801,992, by Higgins, III in U.S. Pat. No. 4,727,410, and by Brown et al in both U.S. Pat. Nos. 4,502,098 and 4,823,233. These three dimensional type packages are used in mid-range systems to gain maximum packaging density and enhance sYstem performance. However, none of these patents or other teachings in the prior art, provide a three dimensional chip package that combines enhanced packaging density with high cooling efficiency.
In fact, the need for cooling efficiency increases as circuit density increases. If not addressed, the lack of proper cooling capacity can have a serious adverse effect on system performance for densely packaged systems.
Accordingly, it would be desirable to have an integrated circuit package which can be efficiently cooled and accommodate high volumetric packaging. The resulting package would be particularly useful in enhancing the system level performance for VLSI computer processors, among other devices.